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| Parallel EEPROMs Compiler Features s Preliminary Flexible Architecture - 16-16K words - Max 64K bits - Support Data Bus width 4-128 bits in 4 bit increments Fast Read Access Time - 100ns Fast Self-Timed Byte Write Cycle - 1ms - Internal Address and Data Latches - Internal Control Timer - Automatic Clear Before Write Fast Self-Timed Write All - 8ms - Automatic Clear Before Write Direct Microprocessor Control - READY/BUSY s s 3.3V 10% Supply Low Power - 5 mA Active Current - 10 A CMOS Standby Current High Reliability - Endurance: 105 Cycles - Data Retention: 10 Years Direct Microprocessor Control - Asynchronous clear - Independent output enables Commercial and Industrial Temperature Ranges Advanced Double Poly Triple Metal Embedded EEPROM Process s s s s s s s s General Description The EEPROM Compiler will generate low-power, high-performance Electrically Erasable and Programmable Read Only Memory with easy to use features. The device is manufactured with ICT's reliable nonvolatile CMOS technology. The EEPROM Compiler is accessed like a static RAM for the read or write cycles without the need of external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. The device includes a method for detecting the end of a write cycle, level detection of RDY/BUSY. Once the end of a write cycle has been detected, a new access for a read or a write can begin. The CMOS technology offers fast access times of 100 ns at low power dissipation. When the chip is deselected the standby current is less than 10 A. Figure 1 Pin Configurations Pin Name A0 - A13* CE OE WE I/O0 - I/O31* RDY/BUSY ALLEN RESET Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy Output Write All Enable RESET Input * number of addresses and I/O's are determined by user specified architecture Integrated Circuit Technology Corp. 2123 Ringwood Avenue San Jose, CA 95131 Tel:(408) 434-0678 Fax:(408) 434-0688 http://www.ictpld.com United Microelectronics Corporation No. 10, Innovation Rd. I, Science-Based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. Tel: 886-3578-2258 Fax: 886-3578-0472 http://www.umc.com.tw 1 04-02-005D EEPROM COMPILER BLOCK DIAGRAM VCC GND OE WE CE ALLEN DATA INPUTS/OUTPUTS I/O0 - I/O31 DATA LATCH INPUT/OUTPUT BUFFERS Y DECODER ADDRESS INPUTS X DECODER 09-13-003A OE, CE, WE, ALLEN LOGIC RESET Y-GATING CELL MATRIX Device Operation READ: The EEPROM is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high impedance state whenever CE or OE is high. This dual line control gives designers increased flexibility in preventing bus contention. BYTE WRITE: Writing data into the EEPROM is similar to writing into a Static RAM. A low pulse on the WE or CE input with ALLEN and OE high and CE or WE low (respectively) initiates a byte write. The address location is latched on the last falling edge of WE (or CE); the new data is latched on the first rising edge. Internally, the device performs a self-clear before write. Once a byte write has been started, it will automatically time itself to completion. READY/BUSY: READY/BUSY output can be used to detect the end of a write cycle. RDY/BUSY is actively pulled low during the write cycle and is released at the completion of the write. WRITE PROTECTION: Inadvertent writes to the device are protected against by holding any one of CE high, RESET low or WE high inhibits byte write cycles. See the operating modes table for NORMAL, ERASE ALL, WRITE ALL operation. Write ALL: Writing data into the EEPROM is similar to writing into a Static RAM. A low pulse on the WE or CE input with ALLEN low and OE high and CE or WE low (respectively) initiates a WRITE ALL. Internally, the device performs a selfclear before write. Once a WRITE ALL has been started, it will automatically time itself to completion. 2 04-02-005D EEPROM COMPILER DC and AC Operating Range EEPROM Operating Temperature (Case) Supply Voltage Commercial Industrial 0C - 70C -40C - 85C 3.3V 10% Operating Modes MODE Read Write(2) Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable WRAL CE VIL VIL VIH X X X VIL OE VIL VIH X(1) X X VIH VIH WE VIH VIL X VIH X X VIL I/O DOUT DIN High Z ALLEN X VIH X X RESET VIH VIH VIH X VIL VIH VIH X High Z High Z X VIL Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current AC Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Condition VIN = 0V to VCC + 1V VI/O = 0V to VCC CE = VCC - 0.3V to VCC + 1.0V Com. CE = 2.0V to VCC + 1.0V f = 5 MHZ; IOUT = 0 mA CE = VIL Ind. Com. Ind. Min Max 10 10 10 2 3 5 5 0.6 Units A A A mA mA mA mA V V 2.0 IOL =600A IOH = -600A 2.0 0.4 V V 3 04-02-005D EEPROM COMPILER AC Read Characteristics Symbol TACC TCE(1) TOE(2) TDF(3)(4) TOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE High to Output Float Output Hold from OE, CE or Address, whichever occurred first (1)(2)(3)(4) EEPROM Min Max 100 100 10 0 0 70 50 Units ns ns ns ns ns AC Read Waveforms ALLEN ADDRESS ADDRESS VALID VIH CE tCE tOE OE tACC tOH tDF OUTPUT Notes: HIGH Z OUTPUT VALID 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. . . 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 09-13-004A Input Test Waveforms and Measurement Level 3.0V AC DRIVING LEVELS 0.0V 1.5V AC MEASUREMENT LEVEL tR, tF < 20 ns 08-13-005A 4 04-02-005D EEPROM COMPILER AC Write Characteristics Symbol tAS, tOES tAH tWP tDS tDH, TOEH tCS, tCH tDB tWC TWCALL Parameter Address, OE Set-up Time Address Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time CE to WE and WE to CE Set-up and Hold Time Time to Device Busy Write Cycle Time Write All Cycle Time Min 10 50 100 50 10 0 Type Max Units ns ns 1000 ns ns ns ns 50 0.5 5 1.0 10 ns ms ms AC Write Waveforms WE Controlled ALLEN VIH OE ADDRESS CE tOES tOEH tAS tAH tCH tCS WE tWP tDS tDH DATA IN RDY/BUSY tWC tDB 09-13-007A CE Controlled ALLEN V IH OE ADDRESS tOES tOEH tAS tAH WE tCS tCH CE tWP tDS DATA IN tDH RDY/BUSY tDB tWC 09-13-008A 5 04-02-005D EEPROM COMPILER Write All Waveforms WE Controlled OE ALLEN tOES tOEH t CE AS t AH tCH t CS WE tWP t DS t DH DATA IN RDY/BUSY tDB tWC ALL 09-13-017A CE Controlled OE ALLEN tOES tOEH tAS tAH WE tCS tCH CE tWP tDS DATA IN tDH READY/BUSY tDB tWC ALL 09-13-018A 6 04-02-005D EEPROM COMPILER Integrated Circuit Technology Corp. 2123 Ringwood Avenue San Jose, CA 95131 Tel:(408) 434-0678 Fax:(408) 434-0688 http://www.ictpld.com United Microelectronics Corporation UMC Group No. 10, Innovation Rd. I, Science-Based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. Tel: 886-3578-2258 Fax: 886-3578-0472 http://www.umc.com.tw 7 04-02-005D EEPROM COMPILER 8 04-02-005D |
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